Generally speaking, computer systems typically include one or more central processor units (CPUs). Each CPU includes many signal paths that convey data between functional units that operate on that data. Such data is typically conveyed using a transfer cycle having a specified timing structure. That timing structure dictates a time period when the data to be transferred will be valid. Accordingly, the data is captured while it is valid and held for a specified amount of time. Such data capture can be performed using a number of edge triggered latches.
Within a CPU, edge triggered latches are commonly implemented using a circuit referred to as a xe2x80x9csense amplifierxe2x80x9d. Sense amplifiers are designed to sense the logic level of a data signal and to output a latched version of that logic level. Because the above mentioned time period is typically specified with respect to a particular clock cycle, an edge triggered latch typically samples or xe2x80x9csensesxe2x80x9d the data on the rising edge of that clock cycle. The data is latched, i.e. held at the output of the sense amplifier, until the falling edge of that clock cycle or until the rising edge of the next clock cycle, depending upon its design. Until the next rising edge of the clock, new data can be asserted on the signal line without affecting the latched data.
An ideal sense amplifier would latch the data immediately upon the rising edge of the associated clock cycle. In practice, however, the latching operation occurs over a finite amount of time during which the data must remain stable. That finite amount of time is defined by xe2x80x9cdata set-upxe2x80x9d and xe2x80x9cdata holdxe2x80x9d timing requirements. Accordingly, the data signal presented to the sense amplifier must satisfy the data set-up and data hold timing requirements in order for the associated logic levels to be properly latched.
The data set-up timing requirement refers to the amount of time that the data must remain stable before the sense amplifier latches it. The data set-up time is typically specified in relation to the rising edge of the above mentioned clock cycle. The data hold timing requirement refers to the amount of time that the data signal must remain stable after the rising edge of that clock cycle.
Prior art sense amplifiers have demonstrated a reduction, or improvement, in the data hold timing requirement at the expense of significantly increased data set-up timing requirements. Accordingly, while the data hold timing requirement has been improved, the overall access cycle time for the sense amplifier is effectively unchanged. Therefore, the rate at which data can be presented to the sense amplifier is also unchanged and, hence, performance is not improved.
The sense amplifier of the present invention provides a considerable reduction of the data hold timing requirement without a concomitant increase in the data set-up timing requirement. Accordingly, the overall access time for that sense amplifier is significantly improved, thereby increasing the rate at which data can be presented to the sense amplifier.
More specifically, a method and apparatus are provided for improving the data hold timing requirement of the sense amplifier by coupling a pass-gate to each of its data input ports. Each pass-gate receives a logic level that has developed on an input data signal. When the data is valid, a control signal is asserted that causes the pass-gate to latch the logic level at the input of the sense amplifier. While that logic level is latched, the sense amplifier can generate a corresponding latched output signal and the data signal can transition to a new logic level. Therefore, the pass-gate maintains the logic level at the input of the sense amplifier for the duration of the data hold timing requirement.
The pass-gate can be a level-sensitive latch that latches said first logic level in response to the assertion level of the control signal. It includes a first transistor having a drain terminal connected to the data signal, a source terminal connected to the sense amplifier and a gate terminal connected to the control signal. That transistor can be a PMOS or NMOS transistor.
Also, the pass-gate can include a second transistor that is connected in parallel with the first transistor. That second transistor can be the opposite type of transistor (NMOS or PMOS) as the first transistor.